Proceedings of the Korea Electromagnetic Engineering Society Conference (한국전자파학회:학술대회논문집)
- 2003.11a
- /
- Pages.136-139
- /
- 2003
Design of the Clock Recovery Circuit for a 40 Gb/s Optical Receiver
40 Gb/s 광통신 수신기용 클락 복원 회로 설계
- Park, Chan-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
- Woo, Dong-Sik (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
- Kim, Kang-Wook (School of Electrical Engineering and Computer Science, Kyungpook National University)
- Published : 2003.11.15
Abstract
A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.