Design and Implementation of Direct Digital Frequency Synthesizer Using Reduced ROM Size Algorithm

ROM 축소 알고리즘을 이용한 직접 디지털 주파수 합성기의 설계 및 구현

In this paper, a DDFS(Direct Digital Frequency Synthesis)chip has been designed focusing on the reduction of ROM size and implemented using FPGA. When calculating the sine value for the input phase value, we used the Taylor series expansion approximation method to reduce the number of addresses of ROM. We also used the piecewise straight line approximation method, ie, the stored value int the ROM is the difference of the sine value and the straight line approximation. Using this method, we could reduce four bits for each ROM data.