대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Lock Time 개선과 Jitter 감소를 위한 전하 펌프 PLL

Charge Pump PLL for Lock Time Improvement and Jitter Reduction

  • 이승진 (경북대학교 대학원 전자공학과) ;
  • 최평 (경북대학교 전자전기컴퓨터학부) ;
  • 신장규 (경북대학교 전자전기컴퓨터학부)
  • Lee, Seung-Jin (Department of Electronics, Graduate School, Kyungpook Nat'l Univ) ;
  • Choi, Pyung (School of Electronical Engineering and Computer Science, Kyungpook Nat'l Univ) ;
  • Shin, Jang-Kyoo (School of Electronical Engineering and Computer Science, Kyungpook Nat'l Univ)
  • 발행 : 2003.07.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

키워드