대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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- Pages.819-822
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- 2003
Cycle 수준의 Control Flow Description에서 합성 가능한 VHDL 기술로의 변환 방법에 관한 연구
A Translation Method from Control Flow Descriptions in cycle-accurate level to Synthesizable RTL VHDL Descriptions
초록
This paper defines an algorithmic description language in cycle-accurate level which can be used to design hardware components. The proposed language is less complex and more flexible than VHDL language. In that the language includes C-like control flow descriptions and brief timing information(i.e. clock cycle boundaries) indicated by 'wait_edge' statements. We generate RTL VHDL codes from the descriptions. The proposed language requires only 10~30% of the # of lines to describe the same functionality compared with RTL VHDL.
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