Logic Circuit Fault Models Detectable by Neural Network Diagnosis

  • Tatsumi, Hisayuki (Department of Computer Science, Tsukuba College of Technology) ;
  • Murai, Yasuyuki (Department of Information and Computer Sciences, Kanagawa Institute of Technology) ;
  • Tsuji, Hiroyuki (Department of Information and Computer Sciences, Kanagawa Institute of Technology) ;
  • Tokumasu, Shinji (Department of Information and Computer Sciences, Kanagawa Institute of Technology) ;
  • Miyakawa, Masahiro (Department of Computer Science, Tsukuba College of Technology)
  • Published : 2003.09.01

Abstract

In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

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