Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference (한국조명전기설비학회:학술대회논문집)
- 2003.11a
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- Pages.343-348
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- 2003
A Design of PFC Circuit for Reducing the Harmonic in Constant Voltage-fed Electronic Ballast Circuit
정전압형 전자식 안정기 회로의 고조파 저감을 위한 PFC회로의 설계
Abstract
In this paper, a PFC(Power Factor Correction) electronic ballast with constant voltage-fed is proposed. The proposed PFC electronic ballast is combined of a High-efficiency boost converter and a conventional half bridge inverter. It is proved that the ripple of input-current and the input-current's harmonic of the proposed PFC electronic ballast are reduced using the voltage divider and soft-switching technique. It is demonstrated that simulation results for 40[W] fluorescent lamp correspond with theoretical analysis
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