A set of self-timed latches for high-speed VLSI

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).