LVDS I/O Cells with Rail-to-Rail Input Receiver

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.