Programmable Digital On-Chip Terminator

  • Kim, Su-Chul (Department of Electronics Engineering University) ;
  • Kim, Nam-Seog (SRAM Design, Memory Division, Samsung Electronics) ;
  • Kim, Tae-Hyung (SRAM Design, Memory Division, Samsung Electronics) ;
  • Cho, Uk-Rae (SRAM Design, Memory Division, Samsung Electronics) ;
  • Byun, Hyun-Guen (SRAM Design, Memory Division, Samsung Electronics) ;
  • Kim, Suki (Department of Electronics Engineering University)
  • Published : 2002.07.01

Abstract

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1% over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

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