대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 ITC-CSCC -3
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- Pages.1547-1550
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- 2002
A Proposal of Programmable Logic Architecture for Reconfigurable Computing
- Iida, Masahiro (Graduate School of Science and Technology, Kumamoto University) ;
- Sueyoshi, Toshinori (Department of Computer Science, Faculty of Engineering Kumamoto University)
- 발행 : 2002.07.01
초록
Reconfigurable computing is a new computing paradigm which has more potential in terms of performance and flexibility. Reconfigurable computing systems are opening a new era in digital signal processing such as multimedia, communication and consumer electronics because they can filter data rapidly and excel at pattern recognition, image process- ing and encryption. Although many reconfigurable computing systems use a conventional programmable device, they carry several serious problems to be solved. This paper proposes a logic block architecture of programmable device suit-able for the reconfigurable computing. Compared to conventional logic blocks, our logic block can improve implementation density, efficiency and speed.
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