Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07a
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- Pages.678-681
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- 2002
Very High-Speed VLSI Architecture of Block LMS Adaptive Digital Filter Using Distributed Arithmetic
- Takahashi, Kyo (Iwate Industrial Technology Junior College) ;
- Tsunekawa, Yoshitaka (Department of Electrical and Electronic Engineering, Faculty of Engineering, Iwate University) ;
- Tayama, Norio (Department of Electrical and Electronic Engineering, Faculty of Engineering, Iwate University)
- Published : 2002.07.01
Abstract
In this paper, we propose a block LMS algorithm using distributed arithmetic (BDA) and a multi-memory block structured BDA (MBDA). Moreover, we propose an effective VLSI architecture of adaptive digital filter using MBDA, and evaluate the sampling rate and output latency.
Keywords