대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 ITC-CSCC -1
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- Pages.357-360
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- 2002
False Paths Elimination in Statistical Static Timing Analysis
- Uehata, Masaki (Dept. of EECE, Chuo University) ;
- Tanaka, Masakazu (Matsushita Electric Industrial Co., Ltd.) ;
- Fukui, Masahiro (Matsushita Electric Industrial Co., Ltd.) ;
- Tsukiyama, Shuji (Dept. of EECE, Chuo University)
- 발행 : 2002.07.01
초록
In this paper, we propose a technique to eliminate 1,he effect of false paths in the calculation of the distribution of the maximum delay of a given CMOS combinatorial circuit, when distributions of interconnect delays and gate switching delays of the circuit are given. The technique can be incorporated into our algorithm for the statistical static timing analysis, which can take correlations of the delays into account.
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