대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 ITC-CSCC -1
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- Pages.149-151
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- 2002
An Implementation of Pipelined Prallel Processing System for Multi-Access Memory System
- Lee, Hyung (Department of Information & Communications Engineering, Chungnam National University) ;
- Cho, Hyeon-Koo (Department of Information & Communications Engineering, Chungnam National University) ;
- You, Dae-Sang (Department of Information & Communications Engineering, Chungnam National University) ;
- Park, Jong-Won (Department of Information & Communications Engineering, Chungnam National University)
- 발행 : 2002.07.01
초록
We had been developing the variety of parallel processing systems in order to improve the processing speed of visual media applications. These systems were using multi-access memory system(MAMS) as a parallel memory system, which provides the capability of the simultaneous accesses of image points in a line-segment with an arbitrary degree, which is required in many low-level image processing operations such as edge or line detection in a particular direction, and so on. But, the performance of these systems did not give a faithful speed because of asynchronous feature between MAMS and processing elements. To improve the processing speed of these systems, we have been investigated a pipelined parallel processing system using MAMS. Although the system is considered as being the single instruction multiple data(SIMD) type like the early developed systems, the performance of the system yielded about 2.5 times faster speed.
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