Distribution of Critical Path Delays in a Combinatorial Circuit

In this paper, we consider how to treat delay-time uncertainties caused by inter-die and intradie variabilities in evaluating the distribution of the critical delay of a CMOS combinatorial circuit, and formulate inter-die variability as a correlation of delays. Then, we propose an algorithm to evaluate the distribution of the critical delay based on the algorithm in ［1] which takes correlations into account. We also show some experimental results to see the effect of the formulation.