Pipelined Scheduling for Dynamically Reconfigurable FPGAs

In order to satisfy the requirement for various applications in an electronic device, many dynamically reconfigurable systems such as FPGAs have been used recently. This paper presents a pipelined scheduling for dynamically reconfigurable systems based on FPGAs. For reconfigurable systems conventional schedulings have reduced processing time by minimizing the number of reconfigurations. However, they are not effective enough for applications including many iterative processes such as digital signal processing. Our approach has been able to increase throughput of iterative applications on dynamically reconfigurable systems by using pipelined scheduling.