대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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- Pages.129-132
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- 2002
고성능 내장형 마이크로프로세서를 위한 분기예측기의 설계 및 성능평가
Branch Predictor Design and Its Performance Evaluation for A High Performance Embedded Microprocessor
- Lee, Sang-Hyuk (Dept. of Electronics Engineering, Korea University) ;
- Kim, Il-Kwan (Dept. of Electronics Engineering, Korea University) ;
- Choi, Lynn (Dept. of Electronics Engineering, Korea University)
- 발행 : 2002.06.01
초록
AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.
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