Hardware Implementation for SEED Cipher Processor of Pipeline Architecture

Pipeline 구조의 SEED 암호화 프로세서 구현 및 설계

This paper designed a cipher process, which used SEED-Algorithm that is totally domestic technique. This cipher processor is implemented by using SEED-cipher-Algorithm and pipeline scheduling architecture. The cipher is 16-round Feistel architecture but we show just 16-round Feistel architecture for brevity in this thesis. Of course, we can get the result of the 16-round processing by addition of control part simply. Furthermore, it has pipelined architecture, so the speed of cipher process is the faster than others when we performed a cipher a lot of data. The schedule-function can performed the two-cipher process simultaneously, such as using two-cipher processors.