A New Low Power High Level Synthesis for DSP

DSP를 위한 새로운 저전력 상위 레벨 합성

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.