SOC 설계를 위한 저전력 32-비트 RISC 프로세서의 재사용 가능한 설계

Resuable Design of 32-Bit RISC Processor for System On-A Chip

  • 이세환 (연세대학교 전기전자공학과 VLSI&CAD연구실) ;
  • 곽승호 (연세대학교 전기전자공학과 VLSI&CAD연구실) ;
  • 양훈모 (연세대학교 전기전자공학과 VLSI&CAD연구실) ;
  • 이문기 (연세대학교 전기전자공학과 VLSI&CAD연구실)
  • 발행 : 2001.06.01

초록

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

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