산술 연산 구조의 VCO를 이용한 3.3V 고주파수 CMOS 주파수 합성기의 설계

Design of a 3.3V high frequency CMOS PLL with an arithmetic functionality VCO

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.