3GPP 규격의 터보 복호기 구현을 위한 SOVA 복호기의 하드웨어 구현

Hardware implementation of a SOVA decoder for the 3GPP complied Turbo code

According to the IMT-2000 specification of 3GPP(3rd Generation Partnership Project) and 3GPP2, Turbo codes is selected as a FEC(forward error correction) code for even higher reliable data communication. In 3GPP complied IMT-2000 system, channel coding under consideration is the selective use of convolutional coding and Turbo codes of 1/3 code rate with 4 constraint length. Suggesting a new path metric normalization method, we achieved a low complexity and high performance SOVA decoder for Turbo Codes, Further more, we analyze the decoding performance with respect to update depth and find out the optimal value of it by using computer simulation. Based on the simulation result, we designed a SOVA decoder using VHDL and implemented it into the Altera EPF10K100GC503FPGA.