STI CMP 공정의 연마시간에 따른 평탄화 특성

Planarization characteristics as a function of polishing time of STI-CMP process

  • 김철복 (대북대학교 전기공학과) ;
  • 서용진 (대북대학교 전기공학과) ;
  • 김상용 (아남 반도체 Fab 사업부) ;
  • 이우선 (조선대학교 전기공학과) ;
  • 장의구 (중앙대학교 전자전자공학부)
  • 발행 : 2001.07.01

초록

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

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