한국음향학회:학술대회논문집 (Proceedings of the Acoustical Society of Korea Conference)
- 한국음향학회 2000년도 하계학술발표대회 논문집 제19권 1호
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- Pages.343-346
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- 2000
다 채널 오디오 이퀄라이저의 ASIC구현을 위한 시분할 공유 곱셈기 구조에 관한 연구
A time-shared multiplier designed for the ASIC implementation of multi-channel audio equalizer
- Kim Chong-Yun (School of Electronics and Electrical Engineering, Chung-Ang University, Electronics and Telecommunications Research Institute) ;
- Lee Jae-Sik (School of Electronics and Electrical Engineering, Chung-Ang University, Electronics and Telecommunications Research Institute) ;
- Kim Jae-Hwa (School of Electronics and Electrical Engineering, Chung-Ang University, Electronics and Telecommunications Research Institute) ;
- Chang Tae-Gyu (School of Electronics and Electrical Engineering, Chung-Ang University, Electronics and Telecommunications Research Institute)
- 발행 : 2000.07.07
초록
This paper presents a filter bank designed for the multi-channel audio equalizer. A time-shared multiplier is also proposed to implement the equalizer with a minimum number of gates when it is synthesized with ASIC or FPGA. Further reduction of the number of required gates is achieved by designing the multiplier based on a cascaded sequential circuit utilizing partial multiplications. The equalizer is realized with FPGA and its real-time operation verifies the reliability and high fidelity of the designed system.
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