Proceedings of the Korean Institute of Information and Commucation Sciences Conference (한국정보통신학회:학술대회논문집)
- 2000.05a
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- Pages.438-441
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- 2000
A CPLD Implementation of Turbo Decoder
Turbo 복호기 CPLD 구현
Abstract
In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.
본 논문에서는 Shannon's Limit 보다 근접한 성능을 나타낼 수 있는 Turbo 부호의 기본 이론과 MAP, Log-MAP 복호알고리즘을 정리하고, 이를 바탕으로 VHDL(Very high speed integrated circuit Hardware Description Language)를 이용하여 Log-MAP Turbo 복호기를 ALTERA 사의 FLEX10k100 CPLD(Complex Programmable Logic Device)에 구현하였다.
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