System Development and IC Implementation of High-performance Image Downscaler using Phase-correction Digital Filters

위상 교정 디지털 필터를 이용한 고성능/고화질 이미지 축소기 시스템 개발 및 IC 구현

  • Lee, Y. (School of Electrical, Electronic, and Computer Eng., Dong-A University) ;
  • O. Moon (School of Electrical, Electronic, and Computer Eng., Dong-A University) ;
  • Lee, H. (School of Electrical, Electronic, and Computer Eng., Dong-A University) ;
  • Lee, B. (School of Electrical, Electronic, and Computer Eng., Dong-A University) ;
  • B. Kang (School of Electrical, Electronic, and Computer Eng., Dong-A University) ;
  • C. Hong (School of Electrical, Electronic, and Computer Eng., Dong-A University)
  • Published : 2000.08.01

Abstract

In this paper, we propose an algorithm, an optimized architecture, and an implementation for an improved performance of image downscaler. The proposed downscaler uses two-dimensional digital filters for horizontal and vertical scalings, respectively. It also improves scaling precisions and decreases the loss of data, compared with the 1/32 scaler 〔1〕. In order to achieve the optimization, the digital filters are implemented by the multiplexer -adder type scheme 〔2〕. The scaler is designed by using the Verilog-HDL. It is synthesized into gates by using the Samsung 0.35 um STD90 TLM library.

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