대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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- Pages.349-352
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- 2000
멀티미디어 처리에 적합한 SIMD 곱셈누적 연산기의 설계
SIMD Multiply-accumulate Unit Design for Multimedia Data Processing
초록
In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35
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