대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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- Pages.132-135
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- 2000
VDSM 공정에서 적용되는 RTL-to-GDS Methodology 검토 및 적용
Review on RTL-GDS Methodology for VDSM Process
초록
We have been aware fer some time. that it is becoming harder to develop ASIC only, using the vendor wire model for the current top-down/bottom-up process. Because VDSM has a much bigger wired delay than cell delay, it is also difficult to reduce development time, as well as time-to-market, while developing several million gate ASIC's. The same is true for high frequency ASIC's with VDSM (which have larger wire delay versus cell delay). Therefore, a solution called “RTS-GDS”, using physical constraints fur SOC with timing met, is being actively discussed. This paper suggests a methodology for SOC development by utilizing a top down flow via CWLM along with discussing potential problems. This paper also provides a design flow, including physical synthesis, DFT, floor plan and CWLM, all of which are relevant to proper SOC development.
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