FLEX 방식 고속 무선호출 단말기 설계 및 구현

Design and Implementation of a High Speed Pager Based on FLEX Protocol

In this paper, we have designed a pager based on the FLEX protocol. The pager consists of a decoder, a MCU, a SPI, and a User interface. The decoder contains the following blocks： synchronizer, de-interleaver, error corrector, packet builder. The decoded data is converted to SPI packets for communication between the MCU and the FLEX decoder. The host MCU is a RISC pipelined architecture, so it processes data at high speed and also sends messages to user interface. We have designed the proposed pager as structural modeling using VHDL language. Then, We simulated and synthesized it using tool of SYNOPSYS corporation.