대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 ITC-CSCC -2
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- Pages.657-660
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- 2000
Calculating Error Reduction with Graph Restructuring in Loop Folding
- Nishitani, Yoshi (Faculty of Engineering Osaka Institute of Technology) ;
- Harashima, Katsumi (Faculty of Engineering Osaka Institute of Technology) ;
- Kutsuwa, Toshirou (Faculty of Engineering Osaka Institute of Technology)
- 발행 : 2000.07.01
초록
This paper proposes a Data-Flow-Graph (DFG) restructuring to reduce calculating errors in loop folding scheduling. The prime cause of calculating error is rounding errors due to the restriction of the operation digit of functional units. This rounding error is increased more by using multipliers than adders, so reducing the number of multiplications and putting off them as much as possible reduce rounding errors. The proposed approach reduces the number of multiplications by restructuring DFG in loop folding.
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