대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 ITC-CSCC -1
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- Pages.379-382
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- 2000
Design of Self-Timed Standard Library and Interface Circuit
- Jung, Hwi-Sung (VLSI & CAD Lab., Dept. of Electronic Engineering Yonsei University) ;
- Lee, Moon-Key (VLSI & CAD Lab., Dept. of Electronic Engineering Yonsei University)
- 발행 : 2000.07.01
초록
We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.
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