대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 ITC-CSCC -1
- /
- Pages.191-194
- /
- 2000
A DESIGN OF MULTIPLE-VALUED SOFT-HARDWARE LOGIC CIRCUITS USING NEURON MOS TRANSISTOR
- M.Fukui (Osaka Institute of Technology) ;
- T.Kutsuwa (Osaka Institute of Technology) ;
- Ha, K.rashima (Osaka Institute of Technology) ;
- K.Kobori (Osaka Institute of Technology)
- 발행 : 2000.07.01
초록
A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.
키워드