Low-Power Decimation Filter Using Approximate Processing with Control of Error in CSD Representation

CSD 표현의 오차를 이용한 Approximate Processing과 이를 이용한 저전력 Decimation Filter의 설계

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.