Design and Implementation of Modified Isolated Double DES Using VHDL

VHDL을 이용한 개선된 Isolated 2중 DES의 설계 및 구현

Conventional double DES has been not only shown to have a vulnerable drawback to attack method called 'Meet-in-the-Middle', but also to be hard to use that it is because software implementation has a number of problem in real time processing. This paper describes the design and implementation of modified Isolated double DES algorithm using VHDL for resolving the above problems. In this approach, we also discuss an efficient method for increasing cipher strength through expansion of key length.