대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1999년도 하계종합학술대회 논문집
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- Pages.397-400
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- 1999
회로 내부 노드를 이용한 BIST의 테스트 시간 감소
Test Time Reduction of BIST Using Internal Nodes of a Circuit
초록
As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.
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