Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1999.06a
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- Pages.377-380
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- 1999
Method for Verification of VHDL Behavioral-level Design
행위 수준의 VHDL 설계 검증 방법
Abstract
This paper proposed a method to detect and locate coding errors in HDL behavioral descriptions (designs). The target coding errors are the ones that the compiler cannot find out. As the method, this paper used verification pattern generation method. Thus, an algorithm to generate the verification patterns was proposed, in which the pattern generation is performed by a path- searching method. Various example designs were applied to this algorithm to verify the correctness and effectiveness of the proposed method.
Keywords