대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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FLEX 방식 고속무선호출 디코더의 VHDL 모델링 및 구현 연구

Study on the VHDL modeling and Implementation of a FLEX high speed pager decoder

  • 박진 (전남대학교 전자공학과) ;
  • 이태원 (전남대학교 전자공학과) ;
  • 김영철 (전남대학교 전자공학과)
  • Park, Jin (Dept. of Electronic. Eng., Chonnam National University) ;
  • Lee, Tae-Won (Dept. of Electronic. Eng., Chonnam National University) ;
  • Kim, Young-Chul (Dept. of Electronic. Eng., Chonnam National University)
  • 발행 : 1999.06.01
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초록

In tills paper, we design it decoder for the FLEX high speed paging protocol. The decoder that we design consists of a synchronizer, a de-interleaver, a error corrector and a packet builder In the FLEX protocol, a word is coded using HCH algorithm. In this design, we do not use a look-up table in order to decrease a chip area of the BCH decoder. The simulation result shows that the decoder is correctly designed

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