Determination of Memory Trap Distribution in Charge Trap Type SONOSFET NVSM Cells Using Single Junction Charge Pumping Method

Single Junction Charge Pumping 방법을 이용한 전하 트랩 형 SONOSFET NVSM 셀의 기억 트랩 분포 결정

  • 양전우 (광운대학교 전자재료공학과) ;
  • 흥순혁 (광운대학교 전자재료공학과) ;
  • 박희정 (광운대학교 전자재료공학과) ;
  • 김선주 (광운대학교 전자재료공학과) ;
  • 서광열 (광운대학교 전자재료공학과)
  • Published : 1999.11.01

Abstract

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

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