An Implementation of Bit Processor for the Sequence Logic Control of PLC

PLC의 시퀀스 제어를 위한 BIT 연산 프로세서의 구현

  • Yu, Young-Sang (Dept. Electronic Engineering, Chongju Univ.) ;
  • Yang, Oh (Dept. Electronic Engineering, Chongju Univ.)
  • 유영상 (청주대학교 이공대학 전자.정보통신.반도체 공학부) ;
  • 양오 (청주대학교 이공대학 전자.정보통신.반도체 공학부)
  • Published : 1999.07.19

Abstract

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

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