An Efficient Delay Calculation Tool for Timing Analysis

타이밍 분석을 위한 효율적인 시간 지연 계산 도구

  • 김준희 (숭실대학교 컴퓨터학부) ;
  • 김부성 (숭실대학교 컴퓨터학부) ;
  • 갈원광 (숭실대학교 컴퓨터학부) ;
  • 맹태호 (숭실대학교 컴퓨터학부) ;
  • 백종흠 (숭실대학교 컴퓨터학부) ;
  • 김석윤 (숭실대학교 컴퓨터학부)
  • Published : 1998.11.28

Abstract

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

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