An Efficient Timing-level Gate-delay Calculation Algorithm

효율적인 타이밍 수준 게이트 지연 계산 알고리즘

In recent years, chip delay estimation has had an increasingly important impact on overall design technology. The analysis of the timing behavior of an ASIC should be based not only on the delay characteristics of gates and interconnect circuits but also on the interactions between them. This model plays an important role in our CAD system to analyze the ASIC timing characteristics accurately, together with two-dimensional gate delay table model, AWE algorithm and effective capacitance concept. In this paper, we present an efficient algorithm which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC-tree and an effective capacitance equation that captures the complete waveform response accurately.