Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Implementation of Reed-Solomon Decoder Using the efficient Modified Euclid Module

효율적 구조의 수정 유클리드 구조를 이용한 Reed-Solomon 복호기의 설계

  • Kim, Dong-Sun (Dept. of Electronic Materials & Device Engineering, INHA Univ.) ;
  • Chung, Duck-Jin (Dept. of Electronic Materials & Device Engineering, INHA Univ.)
  • 김동순 (인하대학교 공과대학 전자재료공학과) ;
  • 정덕진 (인하대학교 공과대학 전자재료공학과)
  • Published : 1998.11.28
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Abstract

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

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