A Simulator for a Five-stage Pipeline DSP core

5단계 파이프라인 DSP 코어를 위한 시뮬레이터의 설계

We designed a DSP core simulator with C language, that is able to simulate 5-stage pipelined DSP core, named YS-DSP. It can emulate all 5 stage pipelines in the DSP core. It can also emulate memory access, exception processing, and DSP parallel processing. Each pipeline stage is implemented by combination of one or more functions to process parts of each stage. After modeling and validating the simulator, we can use it to verify and to complement the DSP core HDL model and to enhance its performance.