Implementation of Ladder Diagram Translator for High-Speed Programmable Logic Controller

프로그램형 논리 제어기의 고속화를 위한 래더 언어 해석기의 구현

  • Kim, Hyung-Seok (Control Information Systems Lab., Seoul National University) ;
  • Kwon, Wook-Hyun (Control Information Systems Lab., Seoul National University)
  • 김형석 (서울대학교 전기공학부 제어정보시스템 연구실) ;
  • 권욱현 (서울대학교 전기공학부 제어정보시스템 연구실)
  • Published : 1998.07.20

Abstract

This paper proposes a translation method that converts ladder diagrams to binary executable codes for PLC (programmable logic controller)s. A PLC based on general purpose DSP(digital signal processor) validates the method. We performed a benchmark on the system that compares the execution time of the interpretation method and ours. Experimenal result shows how fast this method executes programs that consist of codes generated.

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