An improved linear sampled-data output regulators

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In general, the solvability of linear robust output regulation problem are not preserved under time-sampling. Thus, it is found that the digital regulator implemented by itme-sampling of anlog output regulator designed based on the continuous-time linear system model is nothing but a 1st order approximation with respect to time-sampling. By the way, one can design an improved sampled-data regulator with respect to sampling time by utilizing the intrinsic structure of the system. In this paper, we study the system structures which it is possible to design an improved sampled-data regulator with respect to sampling time.