Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Investigation of the Characteristic of Latch-up of 0.1 ${\mu}{\textrm}{m}$ Gate Length CMOS

0.1${\mu}{\textrm}{m}$ 게이트 길이의 CMOS소자의 Latch-up 특성에 대한 연구

  • 김연태 (인하대학교 공과대학 전자재료공학과) ;
  • 원태영 (인하대학교 공과대학 전자재료공학과)
  • Published : 1994.11.01

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Abstract

In this Study, we design the process of 0.1$\mu\textrm{m}$ gate length CMOS that is immunized against Latch-up, and investigate the characteristic of Latch-up of this device by the design rule of layout. Using TSUPREM4 and MEDICI, we design the device and simulate the variable characteristics of it we could understand that the characteristic of Latch-up is changed for the better by varying the critical factor of it. We also investigate the structure of CMOS that can be immunized against Latch-up.

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