제어로봇시스템학회:학술대회논문집

Institute of Control, Robotics and Systems (제어로봇시스템학회)
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A study on the architecture and instruction of a RISC processor for programmable logic controller

PLC용 RISC 프로세서의 구조와 명령어에 관한 연구

  • 구경훈 (서울대학교 공과대학 제어계측공학과) ;
  • 박재현 (서울대학교 공과대학 제어계측공학과) ;
  • 장래혁 (서울대학교 공과대학 제어계측공학과) ;
  • 권욱현 (서울대학교 공과대학 제어계측공학과)
  • Published : 1993.10.01
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Abstract

In this paper, the instruction set and the architecture of a RISC processor for programmable logic controller is suggested. From the measurement of existing programs, the characteristics of ladder instructions are analyzed. The instruction set is defined so that the existing ladder program can be reused with simple translation. Because bit instructions controls the behavior of word instructions, the processor suits for high level language like SFC. Simulations show that the PLC with the suggested processor is twenty times faster than the PLC with the multi-purpose microprocessor.

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