Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1988.07a
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- Pages.574-578
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- 1988
A study on the Testable Design of Domino CMOS NOR-NOR Array Logic
Domino CMOS NOR-NOR Array Logic의 Testable Design에 관한 연구
- Lee, Joong-Ho (Dept. of Electronic and Computer Engineering, university of ulsan) ;
- Cho, Sang-Bock (Dept. of Electronic and Computer Engineering, university of ulsan)
- Published : 1988.07.01
Abstract
This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.
Keywords