Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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16-ns 256K CMOS SRAM

16-ns 256k CMOS SRAM

  • Kim, B.Y. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Jung, T.S. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Park, H.C. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Hwang, S.K. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Park, Y.B. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Kim, C.R. (Samsung Semiconductor & Telecommunication Co., Ltd.) ;
  • Choi, K.H. (Samsung Semiconductor & Telecommunication Co., Ltd.)
  • Published : 1988.07.01
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Abstract

This paper describes 256k (256K ${\times}$1) CMOS SRAM utilizing 1.2um double-polysilicon and double-metal CMOS process. A typical access time of 16ns with a 30-pF load has been achieved through the use of a block architecture, a new decoder, an unique bit-line scheme and an optimized process. Operating current is 55mA at 40MHz and 15mA at 10MHz. A high-resistive polysilicon load has been used to achieve a standby current of 3uA.

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