대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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- Pages.1577-1580
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- 1987
게이트 및 기능 레벨 논리 시뮬레이터
A Gate and Functional Level Logic Simulator
초록
This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.
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