Test Generation Algorithm for CMOS Circuits considering Time - skews

Time-stews를 고려한 CMOS회로의 테스트 생성 알고리즘

This paper proposes a new test generation algorithm to detect stuck-open faults regardless of tine-skews in CMOS circuits. For testing for stuck-open faults regardless of time-skews, in this method, Hamming distance between the initialization pattern and the test pattern is made 1 by considering the responses of the internal gates. Therefore, procedure of the algorithm is simpler than that of the conventional methods because the line justification is unnecessary. Also, this method needs no extra hardware for testability and can be applied to random CMOS circuits in addition to two-level NAND - NAND CMOS circuits.